The present Invention relates, in general, to a novel compound semiconductor insulated gate field effect transistor (IGFET) and to a novel process for making the device.
Indium phosphide (InP) has received increasing attention as a promising semiconductor material in the field of high frequency microwave devices and high speed logic circuits due to its high electron drift velocity. The electron drift velocity for InP is higher than other conventional semiconductors, i.e., silicon (Si) and gallium arsenide (GaAs). Additionally, the use of semi-insulating InP has been found to result in a 100 times reduction in parasitic capacitance as compared to that of conventional p-type substrates.
The microwave frequency and logic speed attainable with a material are roughly proportional to the electron drift velocity. One anticipated use for this material is integration with electro-optic devices. InP has been shown to be an ideal substrate for epitaxial growth of lattice-matched quaternary InGaAsP and ternary InGaAs, both materials used in fabricating electro-optic device structures which operate in the 1.0 to 1.5 micrometer optical wavelength band. Such devices are used to generate optical signals that can be transmitted along optical fibers with very little attenuation and dispersion.
Much work has been directed to developing the fabrication technology and processes required to fabricate InP device structures. The device geometry must be small (one micron or less because of the high speed and high frequency requirements. The speed and frequency of device operation is inversely proportional to the distance traveled by the electrons in the device active region; therefore, submicron device geometries are required.
Planar ion implanted device designs in silicon and other materials have been limited by the ability to define active regions within the crystal material with standard photolithographic techniques. A self-aligned process is often used to avoid critical photolitographic alignment steps. Since the high temperature annealing steps required after the ion-implantation step are detrimental to the InP-insulator interface, the procedures developed for processing self-aligned structures in silicon are not suitable for similar InP strucutres. Due to these problems, prior art InP devices have been non-planar.
The present Invention avoids this problem through the use of a novel "virtual self-aligned" process which results in the production of a novel planar IGFET structure formed on a semi-insulating InP substrate.